I finally got a device working with the UART and was able to capture what happens during boot. Here's the result: DDR Version 1.14 20180803 In Channel 0: LPDDR4,50MHz CS = 0 MR0=0x98 MR4=0x3 MR5=0xFF MR8=0x8 MR12=0x4D MR14=0x4D MR18=0x0 MR19=0x0 MR24=0x8 MR25=0x0 CS = 1 MR0=0x18 MR4=0x3 MR5=0xFF MR8...